QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 158
QG82945GSE S LB2R
Manufacturer Part Number
QG82945GSE S LB2R
Description
GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
Manufacturer
Intel
Datasheet
1.AU80586GE025DSLB73.pdf
(482 pages)
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6.2.68
6.2.69
158
C0DRAMW - Channel 0 DRAM Width
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register determines the width of SDRAM devices populated in each rank of
memory in this channel.
G1SC - Group 1 Strength Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
15:8
7:6
5:4
3:2
1:0
Bit
Access
R/W/L
R/W/L
R/W/L
R/W/L
RO
Default
Value
00b
00b
00b
00b
00b
Reserved
Rank 3 Width:
Width of devices in rank 1
00:16-bit wide devices or unpopulated
01:8-bit wide devices
10:Reserved
11:Reserved
Rank 2 Width:
Width of devices in rank 0
00:16-bit wide devices or unpopulated
01:8-bit wide devices
10:Reserved
11:Reserved
Rank 1 Width:
Width of devices in rank 1 (first DIMM, second side)
00:16-bit wide devices or unpopulated
01:8-bit wide devices
10:Reserved
11:Reserved
Rank 0 Width:
Width of devices in rank 0 (first DIMM, first side)
00:16-bit wide devices or unpopulated
01:8-bit wide devices
10:Reserved
11:Reserved
0/0/0/MCHBAR
40C-40Dh
0000h
R/W/L; RO
16 bits
0/0/0/MCHBAR
410h
44h
R/W/L
8 bits
Description
Device 0 Memory Mapped I/O Register
Datasheet
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