QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 128

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

128
16:16
15:11
10:9
8:4
3:0
Bit
Access
R/W
R/W
R/W
R/W
RO
Default
Value
07h
00b
0Fh
0b
8h
Back-to-Back Read Command Spacing (Different Rank):
This field controls the turnaround time on the DQ bus for Rd-RD
sequence to different ranks in one channel.
The minimum spacing of commands is calculated based on the
formula:
DDR2 = BL/2 + TA
Encoding
0
1
The bigger turnarounds are used in large configurations, where
the difference in total channel delay between the fastest and
slowest DIMM is large.
Memory Clock portion of Read Delay (tRD_Mclks):
tRD is the number of memory clocks from CS# assert to
H_DRDY# assertion on the FSB.
The following tRD_Mclks values are supported:
Reserved
Write Auto Precharge to Activate (Same bank)
(WRAP2ACTSB):
This field determines the clock spacing between write command
with Auto precharge and a subsequent Activate command to
the same bank.
The minimum spacing is calculated based on this formula
DDR2 = CL -1 + BL/2 + tWR + tRP
00h to 03h:Reserved
04h to 15h:Allowed
16h to 1Fh:Reserved
tWR is a DRAM Parameter
Read Auto Precharge to Activate (Same bank)
(RDAP2ACTSB):
This field determines the clock spacing between a read
command with Auto precharge and a subsequent Activate
command to the same bank. 0h: to 2h: Reserved
3h: to Ch: Allowed
Dh: to Fh: Reserved
01000 to 11111: Reserved
00000 – 00010: Reserved
(Sheet 4 of 4)
2 turnaround clocks on DQ
1 turnaround clocks on DQ
Turnaround
00011: 3 mclks
00100: 4 mclks
00101: 5 mclks
00110: 6 mclks
00111: 7 mclks (DDR2 400)
Description
Device 0 Memory Mapped I/O Register
6
5
BL8 CMD Spacing
Datasheet