QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 104

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

5.1.27
104
SMRAM - System Management RAM Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit
is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set.
The SMRAMC register controls how accesses to Compatible and Extended SMRAM
Bit
7
6
5
4
3
Access
R/W/L
R/W/L
R/W/L
R/W
RO
Default
Value
0b
0b
0b
0b
0b
Reserved
SMM Space Open (D_OPEN):
When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made
visible even when SMM decode is not active.
This is intended to help BIOS initialize SMM space. Software
should ensure that D_OPEN=1 and D_CLS=1 are not set at the
same time.
SMM Space Closed (D_CLS):
When D_CLS = 1 SMM space DRAM is not accessible to data
references, even if SMM decode is active. Code references may
still access SMM space DRAM.
This will allow SMM software to reference through SMM space to
update the display even when SMM is mapped over the VGA
range. Software should ensure that D_OPEN=1 and D_CLS=1 are
not set at the same time. Note that the D_CLS bit only applies to
Compatible SMM space.
SMM Space Locked (D_LCK):
When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK,
D_OPEN, C_BASE_SEG, H_SMRAM_EN, GMS, TOLUD, TSEG_SZ,
and TSEG_EN become read only. D_LCK can be set to 1 via a
normal configuration space write but can only be cleared by a Full
Reset. The combination of D_LCK and D_OPEN provide
convenience with security. The BIOS can use the D_OPEN
function to initialize SMM space and then use D_LCK to “lock
down” SMM space in the future so that no application software (or
BIOS itself) can violate the integrity of SMM space, even if the
program has knowledge of the D_OPEN function.
Global SMRAM Enable (G_SMRAME):
If set to a 1, then Compatible SMRAM functions are enabled,
providing 128 KB of DRAM accessible at the A0000h address
while in SMM (ADSB with SMM decode). To enable Extended
SMRAM function this bit has be set to 1. Refer to the sections on
SMM for more details. Once D_LCK is set, this bit becomes read
only.
0/0/0/PCI
9Dh
02h
R/W/L; RO
8 bits
Host Bridge Device 0 - Configuration Registers (D0:F0)
Description
Datasheet