QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 154

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

6.2.59
6.2.60
6.2.61
154
WDLLBYPMODE - Write DLL Bypass Mode Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls WDLL functional and bypass modes for all the buffer types.
C0WDLLCMC - Channel 0 WDLL/Clock Macro Clock Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls WDLL and Macro Clock Control.
C0HCTC - Channel 0 Half Clock Timing Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
7:6
Bit
5
4
3
2
1
0
Access
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
RO
Default
Value
00b
0b
0b
0b
0b
0b
0b
Reserved
Reserved
Clock Half Clock Push Out for DIMM1:
Control Half Clock Push Out for DIMM1:
Setting both CTLQCPI1 and CTLQCPO1 is undefined.
Control Half Clock Push Out for DIMM0:
0: No Push-out.
1: 0.5 system memory clock push-out.
Setting both CTLQCPI0 and CTLQCPO0 is undefined.
Command Half Clock Push Out:
0: No Push-out.
1: 0.5 system memory clock push-out.
Data Half Clock Push Out:
0: No Push-out.
1: 0.5 system memory clock push-out.
0: No Push-out.
1: 0.5 system memory clock push-out.
0: No Push-out.
1: 0.5 system memory clock push-out.
0/0/0/MCHBAR
360-361h
0000h
R/W/L; RO
16 bits
0/0/0/MCHBAR
36C-36Fh
000000FFh
R/W/L; RO
32 bits
0/0/0/MCHBAR
37Ch
00h
R/W/L; RO
8 bits
Description
Device 0 Memory Mapped I/O Register
Datasheet