QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 235

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

PCI Express Graphics Device 1 Configuration Registers (D1:F0)
7.1.12
7.1.13
Datasheet
IOBASE1 - I/O Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the CPU to PCI Express-G I/O access routing based on the
following formula:
IO_BASE <= address <= IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will be
aligned to a 4-KB boundary.
IOLIMIT1 - I/O Limit Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the CPU to PCI Express-G I/O access routing based on the
following formula:
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be
at the top of a 4-KB aligned address block.
7:4
3:0
7:4
3:0
Bit
Bit
IO_BASE=< address =<IO_LIMIT
Access
Access
R/W
R/W
RO
RO
Default
Default
Value
Value
Fh
0h
0h
0h
I/O Address Base (IOBASE):
Corresponds to A[15:12] of the I/O addresses passed by bridge 1
to PCI Express-G*.
accesses will be forwarded to the PCI Express hierarchy
associated with this device.
Reserved
I/O Address Limit (IOLIMIT):
Corresponds to A[15:12] of the I/O address limit of Device 1.
Devices between this upper limit and IOBASE1 will be passed to
the PCI Express hierarchy associated with this device.
Reserved
BIOS must not set this register to 00h otherwise 0CF8h/0CFCh
0/1/0/PCI
1Ch
F0h
R/W; RO
8 bits
0/1/0/PCI
1Dh
00h
R/W; RO
8 bits
Description
Description
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