QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 335

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

System Address Map
9.9.1
Datasheet
address signal is asserted. HAB_16 is asserted on the CPU bus whenever an I/O access
is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. HAB_16 is also asserted
when an I/O access is made to 2 bytes from address 0FFFFh.
A set of I/O accesses (other than ones used for configuration space access) are
consumed by the internal graphics device if it is enabled. The mechanisms for internal
graphics I/O decode and the associated control is explained later.
The I/O accesses (other than ones used for configuration space access) are forwarded
normally to the DMI bus unless they fall within the PCI Express I/O address range as
defined by the mechanisms explained below. I/O writes are not posted. Memory writes
to ICH or PCI Express are posted. The PCICMD1 register can disable the routing of I/O
cycles to PCI Express.
The (G)MCH responds to I/O cycles initiated on PCI Express or DMI with a UR status.
Upstream I/O cycles and configuration cycles should never occur. If one does occur, the
request will route as a read to memory address 0h so a completion is naturally
generated (whether the original request was a read or write). The transaction will
complete with a UR completion status.
For Intel® Pentium® M processor, Intel Core Duo processor, Intel Core Solo processor,
and Mobile Intel® Pentium® 4 processor with 1-MB L2 cache processors, I/O reads
that lie within 8-byte boundaries but cross 4-byte boundaries are issued from the CPU
as 1 transaction. The (G)MCH will break this into two separate transactions. This has
not been done on previous chipsets. I/O writes that lie within 8-byte boundaries but
cross 4-byte boundaries are assumed to be split into two transactions by the CPU.
PCI Express I/O Address Mapping
The (G)MCH can be programmed to direct non-memory (I/O) accesses to the PCI
Express bus interface when CPU initiated I/O cycle addresses are within the PCI
Express I/O address range. This range is controlled via the I/O Base Address (IOBASE)
and I/O Limit Address (IOLIMIT) registers in (G)MCH Device 1 configuration space.
The (G)MCH positively decodes I/O accesses to PCI Express I/O address space as
defined by the following equation:
I/O_Base_Address ≤ CPU I/O Cycle Address ≤ I/O_Limit_Address
The effective size of the range is programmed by the plug-and-play configuration
software and it depends on the size of I/O space claimed by the PCI Express device.
The (G)MCH also forwards accesses to the Legacy VGA I/O ranges according to the
settings in the Device 1 configuration registers BCTRL (VGA Enable) and PCICMD1
(IOAE1), unless a second adapter (monochrome) is present on the DMI Interface/PCI.
The presence of a second graphics adapter is determined by the MDAP configuration
bit. When MDAP is set, the (G)MCH will decode legacy monochrome IO ranges and
forward them to the DMI Interface. The IO ranges decoded for the monochrome
adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3Bah and 3BFh.
Note that the (G)MCH Device 1 I/O address range registers defined above are used for
all I/O space allocation for any devices requiring such a window on PCI Express.
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