QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 223

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6.7.15
Datasheet
EPLE2D - EP Link Entry 2 Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register is the first part of a Link Entry which declares an internal link to another
Root Complex Element.
31:24
23:16
15:2
Bit
1
0
Access
R/WO
R/WO
RO
RO
RO
Default
Value
0000h
02h
00h
1b
0b
Target Port Number (TPN):
Specifies the port number associated with the element targeted
by this link entry (PEG). The target port number is with respect
to the component that contains this element as specified by the
target component ID.
Target Component ID (TCID):
Identifies the physical or logical component that is targeted by
this link entry. A value of 0 is reserved. Component IDs start at
1. This value is a mirror of the value in the Component ID field
of all elements in this component.
This value is a mirror of the value in the Component ID field of
all elements in this component. The value only needs to be
written in one of the mirrored fields and it will be reflected
everywhere that it is mirrored.
Reserved
Link Type (LTYP):
Indicates that the link points to configuration space of the
integrated device which controls the x16 root port.
The link address specifies the configuration address (segment,
bus, device, function) of the target root port.
Link Valid (LV):
0: Link Entry is not valid and will be ignored.
1: Link Entry specifies a valid link.
0/0/0/EPBAR
60-63h
02000002h
R/WO; RO
32 bits
Description
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