QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 221

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6.7.13
Datasheet
EPLE1D - EP Link Entry 1 Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register is the first part of a Link Entry which declares an internal link to another
Root Complex Element.
31:24
23:16
15:2
Bit
1
0
Access
R/WO
R/WO
RO
RO
RO
Default
Value
0000h
01h
00h
0b
0b
Target Port Number (TPN):
Specifies the port number associated with the element targeted
by this link entry (DMI). The target port number is with respect
to the component that contains this element as specified by the
target component ID.
Target Component ID (TCID):
Identifies the physical or logical component that is targeted by
this link entry.
This value is a mirror of the value in the Component ID field of
all elements in this component. The value only needs to be
written in one of the mirrored fields and it will be reflected
everywhere that it is mirrored.
Reserved
Link Type (LTYP):
Indicates that the link points to memory-mapped space (for
RCRB). The link address specifies the 64-bit base address of
the target RCRB.
Link Valid (LV):
0: Link Entry is not valid and will be ignored.
1: Link Entry specifies a valid link.
0/0/0/EPBAR
50-53h
01000000h
R/WO; RO
32 bits
Description
221