QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 26

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QG82945GSE S LB2R

Manufacturer Part Number
QG82945GSE S LB2R
Description
GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
Manufacturer
Intel
Datasheet
1.1.6
1.1.7
1.1.8
1.1.9
26
DMI
Power Management
ISIPP Support
Package
• Chip-to-chip interface between (G)MCH and ICH
• Configurable as x2 or x4 DMI lanes
• DMI lane reversal support
• 2 GB/s (1 GB/s each direction) point-to-point interface to Intel 82801GBM
• 32-bit downstream address
• Direct Media Interface asynchronously coupled to core
• Supports two Virtual Channels for traffic class performance differentiation
• Supports both snooped and non-snooped upstream requests
• Supports isochronous non-snooped traffic
• Supports legacy snooped isochronous traffic
• Supports the following traffic types to or from Intel 82801GBM
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
• ACPI S0, S3, S4, S5
• CPU States C0, C1, C2, C3, C4 states
• PCI Express Link States: L0, L0s, L1, L2, L3
• Intel Rapid Memory Power Management
• HSLPCPU# output
• DPWR# support
• Yes
• FCBGA
• Ball Count: 1466 balls
• Package Size: 37.5 mm x 37.5 mm
• Ball Pitch: 42-mil x 34-mil pitch
DMA, floppy drive, and LPC bus masters
— Peer write traffic between DMI and PCI Express Graphics port
— DMI-to-DRAM
— DMI-to-CPU (FSB Interrupts or MSIs only).
— CPU-to-DMI
— Messaging in both directions, including Intel Vendor-specific messages
— Supports Power Management state change messages
— APIC and MSI interrupt messaging support
— Supports SMI, SCI and SERR error indication
Introduction
Datasheet

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