QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 198
QG82945GSE S LB2R
Manufacturer Part Number
QG82945GSE S LB2R
Description
GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
Manufacturer
Intel
Datasheet
1.AU80586GE025DSLB73.pdf
(482 pages)
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6.5.12
6.5.13
198
UPMC3 Unit Power Management Control 3
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
ECO - ECO Bits
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
32:19
18
17
16
15:0
Bit
R/W; RO 0000000000b
R/W
R/W; RO 0b
R/W
RO
Access
0b
0000h
0h
Default
Value
Reserved
Aux0 Trip Remapping:
1: Aux0 trip for DRAM refresh rate will come from EXTTS0
0: Aux0 trip for DRAM refresh rate will come from EXTTS1
Note: This register should only be set to 1 if Fast C4/C4e
exit has been enabled.
Reserved
Fast C4/C4E Exit Enable:
1 = Enable Fast C4/C4E Exit. (This bit should be used only
if the required implementation exists in hardware; see
Section
0 = Normal Operation (EXTTS1# will be used for thermal
throttling)
Reserved
0/0/0/MCHBAR
FC0-FC3h
00000000h
R/W; RO
32 bits
0/0/0/MCHBAR
FFC-FFFh
00000000h
R/W; RO
32 bits
10.6.7)
Device 0 Memory Mapped I/O Register
Description
Datasheet
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