QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 143

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6.2.31
6.2.32
6.2.33
6.2.34
6.2.35
Datasheet
C1BNKARC - Channel 1 DRAM Bank Architecture
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0BNKARC.
C1DRT0 - Channel 1 DRAM Timing Register 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DRT0.
C1DRT1 - Channel 1 DRAM Timing Register 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DRT1.
C1DRT2 - Channel 1 DRAM Timing Register 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DRT2.
C1DRC0 - Channel 1 DRAM Controller Mode 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DRC0.
0/0/0/MCHBAR
18E-18Fh
0000h
R/W; RO
16 bits
0/0/0/MCHBAR
190-193h
B96038F8h
R/W; RO
32 bits
0/0/0/MCHBAR
194-197h
02607122h
R/W; RO
32 bits
0/0/0/MCHBAR
198-19Bh
800003FFh
R/W; RO
32 bits
0/0/0/MCHBAR
1A0-1A3h
40000802h
R/W; RO
32 bits
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