QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 233

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QG82945GSE S LB2R

Manufacturer Part Number
QG82945GSE S LB2R
Description
GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
Manufacturer
Intel
Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
7.1.8
7.1.9
Datasheet
HDR1 - Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register identifies the header layout of the configuration space. No physical
register exists at this location.
PBUSN1 - Primary Bus Number
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register identifies that this “virtual” host-PCI Express bridge is connected to PCI
Bus 0.
7:0
7:0
Bit
Bit
Access
Access
RO
RO
Default
Default
Value
Value
01h
00h
Header Type Register (HDR):
Returns 01 to indicate that this is a single function device with
bridge header layout.
Primary Bus Number (BUSN):
Configuration software typically programs this field with the
number of the bus on the primary side of the bridge. Since Device
1 is an internal device and its primary bus is always 0, these bits
are read only and are hardwired to 0.
0/1/0/PCI
0Eh
01h
RO
8 bits
0/1/0/PCI
18h
00h
RO
8 bits
Description
Description
233

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