QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 83

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Host Bridge Device 0 - Configuration Registers (D0:F0)
5.1.4
Datasheet
PCISTS - PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This status register reports the occurrence of error events on Device 0’s PCI interface.
Since MCH Device 0 does not physically reside on PCI_A, many of the bits are not
implemented.
15:15
14:14
13:13
12:12
11:11
10:9
8:8
7:7
Bit
Access
R/WC
R/WC
R/WC
RO
RO
RO
RO
RO
Default
Value
00b
0b
0b
0b
0b
0b
0b
1b
Detected Parity Error (DPE):
The MCH does not implement this bit and it is hardwired to a 0.
Writes to this bit position have no effect.
Signaled System Error (SSE):
This bit is set to 1 when the MCH Device 0 generates an SERR
message over DMI for any enabled Device 0 error condition or.
Device 0 error conditions are enabled in the PCICMD and
ERRCMD registers. Device 0 error flags are read/reset from the
PCISTS or ERRSTS registers. Software clears this bit by writing
a 1 to it.
Received Unsupported Request (RURS):
This bit is set when the MCH generates a DMI request that
receives a Unsupported request completion. Software clears this
bit by writing a 1 to it.
Received Completion Abort Status (RCAS):
This bit is set when the MCH generates a DMI request that
receives a completion abort. Software clears this bit by writing a
1 to it.
Signaled Target Abort Status (STAS):
The MCH will not generate a Target Abort DMI completion
packet or Special Cycle. This bit is not implemented in the MCH
and is hardwired to a 0. Writes to this bit position have no
effect.
DEVSEL Timing (DEVT):
These bits are hardwired to 00. Writes to these bit positions
have no affect. Device 0 does not physically connect to PCI_A.
These bits are set to 00 (fast decode) so that optimum DEVSEL
timing for PCI_A is not limited by the MCH.
Master Data Parity Error Detected (DPD):
PERR signaling and messaging are not implemented by the MCH
therefore this bit is hardwired to 0. Writes to this bit position
have no effect.
Fast Back-to-Back (FB2B):
This bit is hardwired to 1. Writes to these bit positions have no
effect. Device 0 does not physically connect to PCI_A. This bit is
set to 1 (indicating fast back-to-back capability) so that the
optimum setting for PCI_A is not limited by the MCH.
0/0/0/PCI
06-07h
0090h
R/WC; RO
16 bits
(Sheet 1 of 2)
Description
83