QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 374

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

10.5.2.4.2
10.5.2.4.3
10.5.3
10.5.3.1
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Source color keying/ChromaKeying is used to handle transparency based on the
overlay window on a pixel by pixel basis. This is used when “blue screening” an image
to overlay the image on a new background later.
Gamma Correction
To compensate for overlay color intensity loss due to the non-linear response between
display devices, the overlay engine supports independent gamma correction. This
allows the overlay data to be converted to linear data or corrected for the display
device when not blending.
YUV to RGB Conversion
The format conversion can be bypassed in the case of RGB source data. The format
conversion assumes that the YUV data is input in the 4:4:4 format and uses the full
range scale.
Display Pipes
The display consists of two pipes:
A pipe consists of a set of combined planes and a timing generator. The timing
generators provide the basic timing information for each of the display pipes. The
(G)MCH has two independent display pipes, allowing for support of two independent
display streams. A port is the destination for the result of the pipe.
Pipe A can operate in a single-wide or “double-wide” mode. In double-wide mode, the
pipe transfers data at 2x graphics core clock though it is effectively limited by the
perspective display port. The display planes and the cursor plane will provide a “double
wide” mode to feed the pipe.
Clock Generator Units (DPLL)
The clock generator units provide a stable frequency for driving display devices. It
operates by converting an input reference frequency into an output frequency. The
timing generators take their input from internal DPLL devices that are programmable to
generate pixel clocks in the range of 25-350 MHz. Accuracy for VESA timing modes is
required to be within ± 0.5%.
The DPLL can take a reference frequency from the external reference input
(DREFCLKINN/P), or the TV clock input (TVCLKIN).
• Display Pipe A
• Display Pipe B
Functional Description
Datasheet