QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 116

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QG82945GSE S LB2R

Manufacturer Part Number
QG82945GSE S LB2R
Description
GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
Manufacturer
Intel
Datasheet
Table 4.
116
Reserved
DQS Master Timing
Reserved
RCVENOUTB Master Timing
Reserved
Channel 0 WL0 RCVENOUT Slave
Timing
Channel 0 WL1 RCVENOUT Slave
Timing
Channel 0 WL2 RCVENOUT Slave
Timing
Channel 0 WL3 RCVENOUT Slave
Timing
Reserved
Write DLL Bypass Mode Control
Channel 1 WL0 RCVENOUT Slave
Timing
Channel 1 WL1 RCVENOUT Slave
Timing
Channel 1 WL2 RCVENOUT Slave
Timing
Channel 1 WL3 RCVENOUT Slave
Timing
Channel 1 WL0 RCVENOUT Slave
Timing
Reserved
C1WDLLCMC - Channel 1 WDLL/
Clock Macro Clock Control
Reserved
Channel 1 Half Clock Timing Control C1HCTC
Reserved
Reserved
Channel 0 WDLL/Clock Macro Clock
Control
Reserved
Channel 0 Half Clock Timing Control
Reserved
Register Name
Device 0 MCHBAR Chipset Control Registers (Sheet 4 of 6)
DQSMT
RCVENMT
C0WL0REOST
C0WL1REOST
C0WL2REOST
C0WL3REOST
WDLLBYPMODE
C0WDLLCMC
C0HCTC
C1WL0REOST
C1WL1REOST
C1WL2REOST
C1WL3REOST
C1WL0REOST
Register
Symbol
2A1
2F4
2F6
2F8
2FC
340
341
342
343
344
360
362
36C
370
37C
37D
3C0
3C1
3C2
3C3
3C0
3C1
3EC
3F0
3FC
3FD
Register
Start
2AB
2F5
2F7
2FB
33F
340
341
342
343
35F
361
36B
36F
37B
37C
3BF
3C0
3C1
3C2
3C3
3C0
3EF
3FB
3FC
3FF
Register
End
Device 0 Memory Mapped I/O Register
0007h
0000070Fh
00h
00h
00h
00h
000000FFh
00h
00h
00h
00h
00h
00h
0000009Fh
00h
0000h
Default
Value
R/W/L
R/W/L; RO
R/W/L; RO
R/W/L; RO
R/W/L; RO
R/W/L; RO
R/W/L; RO
R/W/L; RO
R/W/L; RO
R/W/L; RO
R/W/L; RO
R/W/L; RO
R/W/L; RO
R/W/L; RO
R/W/L; RO
R/W/L; RO
Access
Datasheet

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