QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 239

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

PCI Express Graphics Device 1 Configuration Registers (D1:F0)
7.1.18
7.1.19
Datasheet
PMLIMIT1 - Prefetchable Memory Limit Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register in conjunction with the corresponding Upper Limit Address register
controls the CPU to PCI Express-G prefetchable memory access routing based on the
following formula:
PREFETCHABLE_MEMORY_BASE <= address <= PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 32-bit address. This register must be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be
FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1-MB
aligned memory block. Note that prefetchable memory range is supported to allow
segregation by the configuration software between the memory ranges that must be
defined as UC and the ones that can be designated as a USWC (i.e., prefetchable) from
the CPU perspective.
CAPPTR1 - Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The capabilities pointer provides the address offset to the location of the first entry in
this device's linked list of capabilities.
15:4
3:0
Bit
7:0
Bit
Access
Access
R/W
RO
RO
Default
Default
Value
Value
88h
000h
0h
First Capability (CAPPTR1):
The first capability in the list is the Subsystem ID and Subsystem
Vendor ID Capability.
Prefetchable Memory Address Limit (PMLIMIT):
Corresponds to A[31:20] of the upper limit of the address range
passed to PCI Express-G*.
Reserved
0/1/0/PCI
26-27h
0001h
R/W; RO
16 bits
0/1/0/PCI
34h
88h
RO
8 bits
Description
Description
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