QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 126

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

126
23:22
Bit
Access
R/W
Default
Value
01b
Back-to-Back Write-Read Command Spacing (Different
Rank):
This field determines the number of turnaround clocks on the
data bus that needs to be inserted between write command
and a subsequent read command.
The minimum spacing of commands is calculated based on the
formula:
DDR2 = BL/2 + TA - 1
(
Derived from:
)
BL is the burst length which is 8
TA is the required write to read DQ turnaround on the bus. Can
be set to 1,2, or 3 CK using this register
CL is CAS Latency
Encoding
00
01
10
11
DDR2 = BL/2 + TA (wr-rd) + WL - CL which gives
DDR2 = BL/2 + TA + CL - 1 - CL
(Sheet 2 of 4)
Description
BL8 CMD Spacing
Device 0 Memory Mapped I/O Register
6
5
4
Reserved
Datasheet