QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 315

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Internal Graphics Device 2 Configuration Register (D2:F0-F1)
8.2.26
Datasheet
LBB - Legacy Backlight Brightness
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register can be accessed by byte, word, or dword PCI configuration cycles. A write
to this register will cause the Backlight Event (Display B Interrupt) if enabled.
31:24
23:16
15:8
7:0
Bit
Access
R/W
R/W
R/W
R/W
Default
Value
N/A
N/A
N/A
N/A
LBPC Scratch Trigger3:
When written, this scratch byte triggers an interrupt when LBEE is
enabled in the Pipe B Status register and the Display B Event is
enabled in IER and unmasked in IMR, etc. If written as part of a
16-bit or 32-bit write, only one interrupt is generated in common.
LBPC Scratch Trigger2:
When written, this scratch byte triggers an interrupt when LBEE is
enabled in the Pipe B Status register and the Display B Event is
enabled in IER and unmasked in IMR etc. If written as part of a
16-bit or 32-bit write, only one interrupt is generated in common.
LBPC Scratch Trigger1:
When written, this scratch byte triggers an interrupt when LBEE is
enabled in the Pipe B Status register and the Display B Event is
enabled in IER and unmasked in IMR etc. If written as part of a
16-bit or 32-bit write, only one interrupt is generated in common.
Legacy Backlight Brightness (LBES):
The value of 0 is the lowest brightness setting and 255 is the
brightest. A write to this register will cause a flag to be set (LBES)
in the PIPEBSTATUS register and cause an interrupt if Backlight
event in the PIPEBSTATUS register and cause an Interrupt if
Backlight Event (LBEE) and Display B Event is enabled by
software.
0/2/1/PCI
F4-F7h
00000000h
R/W
32 bits
Description
315