QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 177

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6.4.9
Datasheet
TSTTP1-2 – Thermal Sensor Temperature Trip Point 1-2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register sets the target values for some of the trip points in the Thermometer
mode. See also TSTTP1.
31:31
30:16
15:8
2:2
1:1
0:0
Bit
7:0
Bit
Access
Access
R/W/L
R/W/L
R/WC
R/WC
R/WC
R/WO
RO
Default
Default
Value
Value
0000h
00h
00h
0b
0b
0b
0b
1 = Indicates that an Aux Thermal Sensor trip event occurred
based on a lower to higher temperature transition through the
trip point.
0 = No trip for this event, software must write a 1 to clear this
status bit.
1 = Indicates that an Aux1 Thermal Sensor trip event occurred
based on a lower to higher temperature transition through the
trip point.
0 = No trip for this event, software must write a 1 to clear this
status bit.
Reserved
Aux0 Thermal Sensor Interrupt Event:
Aux1 Thermal Sensor Interrupt Event:
Lock Bit for Aux0, Aux1 Trip Points:
This bit, when written to a 1, locks the Aux x trip point settings.
This lock is reversible. The reversing procedure is: following
sequence must be done in order without any other configuration
cycles in-between:
write testtp2 04C1C202
write testtp2x 04C1C202
write testtp2x 04C1C202
write testtp2 04C1C202
It is expected that the Aux x trip point settings can be changed
dynamically when this lock is not set.
Reserved
Reserved
Aux1 Trip Point Setting (A1TPS):
Sets the target value for the Aux1 trip point.
Lockable by TSTTP2-1 [31].
0/0/0/MCHBAR
C9C-C9Fh
00000000h
R/WO; R/W/L; RO
32 bits
Description
Description
177