QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 77

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

(G)MCH Configuration Process and Registers
4.4.2
Datasheet
CONFIG_DATA—Configuration Data Register
I/O Address:
Size:
CONFIG_DATA is a 32-bit read/write window into configuration space. The portion of
configuration space that is referenced by CONFIG_DATA is determined by the contents
of CONFIG_ADDRESS.
10:8
31:0
7:2
1:0
Bit
Bit
0000 0000 h
Access &
Default
Access &
Default
000b
R/W
R/W
00h
00b
RO
R/W
Function Number:
This field allows the configuration registers of a particular function in a
multi-function device to be accessed. The (G)MCH ignores Configuration
Cycles to its internal Devices if the function number is not equal to 0 or 1.
This field is mapped to byte 6 [2:0] of the request header format during
PCI Express and DMI Configuration Cycles.
Register Number:
This field selects one register within a particular Bus, Device, and
Function as specified by the other fields in the Configuration Address
register.
This field is mapped to byte 7 [7:2] of the request header format for
during PCI Express and DMI Configuration Cycles.
Reserved
Configuration Data Window (CDW):
If bit 31 of CONFIG_ADDRESS is 1, any I/O access to the
CONFIG_DATA register will produce a configuration transaction using
the contents of CONFIG_ADDRESS to determine the bus, device,
function, and offset of the register to be accessed.
§
0CFCh
32 bits
(Sheet 2 of 2)
Description
Description
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