QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 344

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

10.2.5
Note:
Note:
Table 28.
344
DRAM Address Mapping
The
945GM/GME/PM/GMS/GSE, 943/940GML and Intel 945GT Express Chipsets in the
Dual-channel mode without Enhanced
Address Mapping with Enhanced Address Swap.
Address Mapping with Enhanced Address XOR configurations.
For DRAM address mapping on the Ultra Mobile Intel 945GU Express Chipset, refer to
Figure
Enhanced Addressing swaps the MSB controlling one of the Bank Select lines with bit
18 (which normally controls row address bit 2). Without Enhanced Addressing, rank
bits are the most significant two bits of the address. With Enhanced Addressing, the
rank bits are always bits 19 and 20.
In the tables below,
Different ranks may use different technologies or organizations, and it is recommended
to check the DRB register programming to determine which channel and rank an
address belongs to.
Both s and h are provided for the example of a homogenous population only. Column
bit 10 is always used for an Auto Precharge indication.
The Mobile Intel 943/940GML Express Chipset does not support Enhanced Addressing
modes.
The mapping detailed below applies to Single-Channel modes of operation also, except
for symmetric addressing.
DRAM Device Configurations –Single-channel/Dual-channel
Asymmetric Mode (Sheet 1 of 2)
Technology (Mb)
Row Bits
Column Bits
Bank Bits
Width (b)
Rows
Columns
Banks
Page Size (KB)
Devices per Rank
Rank Size (MB)
Depth (M)
Table 28
— ‘r’ indicates a Row Address bit,
— ‘b' indicates a Bank Select bit,
— ‘c’ indicates a Column Address bit,
— ‘h’ indicates a Channel Select bit,
— ‘s’ indicates that the bit is part of the decode for a Chip Select (rank select) bit
28,
Figure
and
30, and
Table 29
Figure
8192
below show the DRAM Address Mapping on the Mobile Intel
256
512
128
13
16
16
9
2
4
4
4
32.
8192
1024
256
256
13
10
32
2
8
4
8
8
Addressing.Table 30
8192
1024
512
256
13
10
16
32
2
4
8
4
Table 32
16384
1024
512
512
14
10
64
2
8
4
8
8
and
1024
8192
1024
and,
512
13
10
16
64
3
8
8
4
Table 33
Table 31
16384
1024
1024
1024
128
14
10
Functional Description
3
8
8
8
8
shows the
show the
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