QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 334

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Table 21.
9.7.3
9.7.4
9.8
9.9
334
SMM Control Table
SMM Space Decode and Transaction Handling
Only the CPU is allowed to access SMM space. PCI Express and DMI originated
transactions are not allowed to SMM space.
CPU WB Transaction to an Enabled SMM Address Space
CPU Writeback transactions (REQ[1]# = 0) to enabled SMM address space must be
written to the associated SMM DRAM even though D_OPEN=0 and the transaction is
not performed in SMM mode. This ensures SMM space cache coherency when cacheable
extended SMM space is used.
Memory Shadowing
Any block of memory that can be designated as read-only or write-only can be
“shadowed” into (G)MCH DRAM memory. Typically this is done to allow ROM code to
execute more rapidly out of main DRAM. ROM is used as read-only during the copy
process while DRAM at the same time is designated write-only. After copying, the
DRAM is designated read-only so that ROM is shadowed. CPU bus transactions are
routed accordingly.
I/O Address Space
The (G)MCH does not support the existence of any other I/O devices beside itself on
the CPU bus. The (G)MCH generates either DMI or PCI Express bus cycles for all CPU I/
O accesses that it does not claim. Within the host bridge the (G)MCH contains two
internal registers in the CPU I/O space, Configuration Address register
(CONFIG_ADDRESS) and the Configuration Data register (CONFIG_DATA). These
locations are used to implement a configuration space access mechanism.
The CPU allows 64 k+3 bytes to be addressed within the I/O space. The (G)MCH
propagates the CPU I/O address without any translation on to the destination bus and
therefore provides addressability for 64 k+3 byte locations. Note that the upper three
locations can be accessed only during I/O address wrap-around when CPU bus HAB_16
G_SMRAME
0
1
1
1
1
1
1
1
1
D_LCK
x
0
0
0
0
0
1
1
1
D_CLS
X
X
X
0
0
1
1
0
1
D_OPEN
x
0
0
1
0
1
x
x
x
CPU in SMM
Mode
x
0
1
x
1
x
0
1
1
SMM Code
Access
Disable
Disable
Disable
Enable
Enable
Enable
Invalid
Enable
Enable
System Address Map
SMM Data
Access
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Invalid
Enable
Datasheet