QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 4

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

3
4
5
4
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
(G)MCH Register Description ...................................................................................67
3.1
(G)MCH Configuration Process and Registers ...........................................................69
4.1
4.2
4.3
4.4
Host Bridge Device 0 - Configuration Registers (D0:F0) ...........................................79
5.1
2.1.2
DDR2 DRAM Interface ........................................................................................40
2.2.1
2.2.2
2.2.3
2.2.4
PCI Express-Based Graphics Interface Signals .......................................................44
2.3.1
DMI – MCH to ICH Serial Interface .......................................................................46
Integrated Graphics Interface Signals ...................................................................46
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
PLL Signals .......................................................................................................51
Reset and Miscellaneous Signals ..........................................................................52
Platform Power Planes ........................................................................................53
Power and Ground .............................................................................................53
Reset States and Pull-up / Pull-downs...................................................................55
2.10.1 Host Interface Signals .............................................................................55
2.10.2 Host Interface Reference and Compensation...............................................56
2.10.3 DDR2 SDRAM Channel A Interface ............................................................57
2.10.4 DDR2 SDRAM Channel B Interface ............................................................58
2.10.5 DDR2 Common Signals............................................................................58
2.10.6 DDR SDRAM Reference and Compensation .................................................59
2.10.7 PCI Express-Based Graphics Interface Signals
2.10.8 PCI Express-Based Graphics Interface Signals
2.10.9 DMI ......................................................................................................61
2.10.10CRT DAC SIGNALS ..................................................................................62
2.10.11Analog TV-out Signals .............................................................................62
2.10.12LVDS Signals .........................................................................................63
2.10.13Display Data Channel (DDC) and GMBUS Support .......................................64
2.10.14PLL Signals ............................................................................................64
2.10.15Reset and Miscellaneous Signals ...............................................................65
Register Terminology .........................................................................................67
Platform Configuration Structure..........................................................................69
Routing Configuration Accesses ...........................................................................70
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
(G)MCH Register Introduction..............................................................................75
I/O Mapped Registers.........................................................................................75
4.4.1
4.4.2
Device 0 Configuration Registers..........................................................................79
Host Interface Reference and Compensation...............................................39
DDR2 SDRAM Channel A Interface ............................................................40
DDR2 SDRAM Channel B Interface ............................................................41
DDR2 Common Signals............................................................................42
DDR2 SDRAM Reference and Compensation ...............................................43
Serial DVO and PCI Express-Based Graphics Signal Mapping.........................45
CRT DAC SIGNALS ..................................................................................46
Analog TV-out Signals .............................................................................47
LVDS Signals .........................................................................................48
Serial DVO Interface ...............................................................................49
Display Data Channel (DDC) and GMBUS Support .......................................50
(PCIe x16 Mode).....................................................................................59
(SDVO Mode) .........................................................................................60
Standard PCI Bus Configuration Mechanism................................................70
Logical PCI Bus 0 Configuration Mechanism ................................................71
Primary PCI and Downstream Configuration Mechanism ...............................71
PCI Express Enhanced Configuration Mechanism .........................................72
(G)MCH Configuration Cycle Flowchart.......................................................74
CONFIG_ADDRESS—Configuration Address Register ....................................76
CONFIG_DATA—Configuration Data Register ..............................................77
Datasheet