QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 260

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

7.1.42
260
RCTL - Root Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register allows control of PCI Express Root Complex specific parameters. The
system error control bits in this register determine if corresponding SERRs are
generated when our device detects an error (reported in this device's Device Status
register) or when an error message is received across the link. Reporting of SERR as
controlled by these bits takes precedence over the SERR Enable in the PCI Command
register.
15:4
Bit
3
2
1
0
Access
R/W
R/W
R/W
R/W
RO
Default
Value
000h
0b
0b
0b
0b
Reserved
PME Interrupt Enable (PMEIE):
messages.
message as reflected in the PME Status bit of the Root Status
register. A PME interrupt is also generated if the PME Status bit of
the Root Status register is set when this bit is set from a cleared
state.
System Error on Fatal Error Enable (SEFEE):
Controls the Root Complex's response to fatal errors.
is reported by any of the devices in the hierarchy associated with
this Root Port, or by the Root Port itself.
System Error on Non-Fatal Uncorrectable Error Enable
(SENFUEE):
Controls the Root Complex's response to non-fatal errors.
error is reported by any of the devices in the hierarchy associated
with this Root Port, or by the Root Port itself.
System Error on Correctable Error Enable (SECEE):
Controls the Root Complex's response to correctable errors.
error is reported by any of the devices in the hierarchy associated
with this Root Port, or by the Root Port itself.
0: No interrupts are generated as a result of receiving PME
1: Enables interrupt generation upon receipt of a PME
0: No SERR generated on receipt of fatal error.
1: Indicates that an SERR should be generated if a fatal error
0: No SERR generated on receipt of non-fatal error.
1: Indicates that an SERR should be generated if a non-fatal
0: No SERR generated on receipt of correctable error.
1: Indicates that an SERR should be generated if a correctable
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
0/1/0/PCI
BC-BDh
0000h
R/W; RO
16 bits
Description
Datasheet