QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 156

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

6.2.66
6.2.67
156
C1WDLLCMC - Channel 1 WDLL/Clock Macro Clock Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls WDLL and Macro Clock Control.
C1HCTC - Channel 1 Half Clock Timing Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
7
6
5
4
3
2
1
0
Access
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
RO
Default
Value
0b
0b
0b
0b
0b
0b
0b
0b
Reserved
Reserved
Reserved
Clock Half Clock Push Out:
0: No Push-out.
1: 0.5 system memory clock push-out.
Control Half Clock Push Out for DIMM1:
0: No Push-out.
1: 0.5 system memory clock push-out.
Setting both CTLQCPI1 and CTLQCPO1 is undefined.
Control Half Clock Push Out for DIMM0:
0: No Push-out.
1: 0.5 system memory clock push-out.
Setting both CTLQCPI0 and CTLQCPO0 is undefined.
Command Half Clock Push Out:
0: No Push-out.
1: 0.5 system memory clock push-out.
Data Half Clock Push Out:
0: No Push-out.
1: 0.5 system memory clock push-out.
0/0/0/MCHBAR
3EC-3EFh
0000009Fh
R/W/L; RO
32 bits
0/0/0/MCHBAR
3FCh
00h
R/W/L; RO
8 bits
Description
Device 0 Memory Mapped I/O Register
Datasheet