QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 113

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6
Note:
6.1
6.2
Table 4.
Datasheet
Reserved
Front Side Bus Power Management
Control 3
Front Side Bus Power Management
Control 4
FSB Snoop Control
Reserved
CPU Sleep Timing Control
Channel 0 DRAM Rank Boundary 0
Channel 0 DRAM Rank Boundary 1
Channel 0 DRAM Rank Boundary 2
Channel 0 DRAM Rank Boundary 3
Reserved
Channel 0 DRAM Rank 0,1 Attribute
Channel 0 DRAM Rank 2,3 Attribute
Reserved
Channel 0 DRAM Clock Disable
Reserved
Register Name
Device 0 Memory Mapped I/O
Register
All accesses to the memory mapped registers must be made as a single dword (4
bytes) or less. Access must be aligned on a natural boundary.
Device 0 Memory Mapped I/O Registers
A variety of timing and control registers have been moved to MMR space of Device 0
due to space constraints.
To simplify the read/write logic to the SRAM, BIOS is required to write and read 32-bit
aligned dwords. The SRAM includes a separate Write Enable for every dword.
The BIOS read/write cycles are performed in a memory mapped IO range that is setup
for this purpose in the PCI configuration space, via standard PCI range scheme.
Device 0 MCHBAR Chipset Control Registers
Device 0 MCHBAR Chipset Control Registers (Sheet 1 of 6)
FSBPMC3
FSBPMC4
FSBSNPCTL
SLPCTL
C0DRB0
C0DRB1
C0DRB2
C0DRB3
C0DRA0
C0DRA2
C0DCLKDIS
Register
Symbol
00
40
44
48
4C
90
100
101
102
103
104
108
109
109
10C
10D
Register
Start
39
43
47
8F
100
101
102
103
107
108
109
10B
10C
10D
4B
93
Register
End
00000000h
00000000h
80800000h
00005055h
00h
00h
00h
00h
00h
00h
00h
Default
Value
R/W; RO
R/W; RO
R/W; RO
R/W; RO
R/W
R/W
R/W
R/W
R/W; RO
R/W; RO
R/W; RO
Access
113