QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 110

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

110
51:48
47:44
43:41
37:36
Bit
40
39
38
35
Access
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
000b
00b
0h
0h
0b
0b
0b
0b
Reserved
Reserved
Render Core Frequency Capability:
000: 400-MHz operation (Intel 945GT Express Chipset)
010: 250-MHz operation (Mobile Intel 945GM/GME/GMS/GSE
Express Chipset)
100: 166 MHz operation (Mobile Intel 943/940GML/GU
Express Chipset)
Others: Reserved
Note: Mobile Intel 945GMS/GSE Express Chipset render clock
capability is set to 250 MHz but SW must program the render
frequency to supported values, i.e., 166 MHz
Note: Ultra Mobile Intel 945GU Express Chipset render clock
capability is set to 250 MHz but SW must program the render
frequency to supported values, i.e., 133 MHz
Reserved
Serial Digital Video Out Capable:
0: (G)MCH capable of serial digital video output. (Mobile Intel
945GM/GME/GMS/GU/GSE, 943/940GML and Intel 945GT
Express Chipset)
1: (G)MCH not capable of serial digital video output. (Mobile
Intel 945PM Express Chipset)
Internal Graphics Capable:
0: There is a graphics engine within this (G)MCH. Internal
Graphics Device (Device 2) is enabled and all of its memory
and I/O spaces are accessible. Configuration cycles to Device 2
will be completed within the (G)MCH. All non-SMM memory
and IO accesses to VGA will be handled based on Memory and
IO enables of Device 2 and IO registers within Device 2 and
VGA Enable of the PCI-to-PCI bridge control register in Device
1 (If PCI Express GFX attach is supported). A selected amount
of Graphics Memory space is pre-allocated from the main
memory based on Graphics Mode Select (GMS in the (G)MCH
Control register). Graphics Memory is pre-allocated above
TSEG Memory.
(Mobile Intel 945GM/GME/GMS/GU/GSE, 943/940GML and
Intel 945GT Express Chipset)
1: There is no graphics engine within this (G)MCH. (Mobile
Intel 945PM Express Chipset)
Reserved
Concurrent PCI-E and SDVO Disable:
Controls whether concurrent use of PCI-E Graphics Port and
SDVO is allowed.
0: Concurrent PCIe and SDVO is allowed.
1: Concurrent PCIe and SDVO is not allowed. PCIe
functionality on the Externa GFX port is disabled if SDVO is
present.
Forces concurrent PCIe/SDVO strap deasserted if SDVO
present strap is sampled asserted.
Host Bridge Device 0 - Configuration Registers (D0:F0)
Description
Datasheet