QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 90

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

5.1.14
90
PCIEXBAR - PCI Express Register Range Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This is the base address for the PCI Express configuration space. This window of
addresses contains the 4 KB of configuration space for each PCI Express device that
can potentially be part of the PCI Express hierarchy associated with the (G)MCH. There
is no actual physical memory within this address range (64 MB, 128 MB, or 256 MB)
window that can be addressed. Each PCI Express hierarchy requires a PCI Express
BASE register. The (G)MCH supports one PCI Express hierarchy.
The address range reserved by this register does not alias to any conventional PCI 2.3-
compliant memory mapped space.
On reset, this register is disabled and must be enabled by writing a 1 to bit[0] of this
register.
The PCI Express Base Address [bits 15:12] must never be set to 0Fh because this
would result in PCI Express configuration space overlapping the HSEG space required
for the Intel® Pentium® 4 processor to respond to interrupts and system management
events. The PCI Express Base Address cannot be below the address written to the top
of low usable dram register (TOLUD).
31:28
Bit
Access
R/W/L
Default
Value
1110b
PCI Express* Base Address:
This field corresponds to bits 31 to 28 of the base address for
PCI Express enhanced configuration space.
BIOS will program this register resulting in a base address for a
256-MB block of contiguous memory address space. Having
control of those particular 4 bits insures that this base address
will be on a 256-MB boundary, above the lowest 256 MB and still
within total addressable memory space, currently 4 GB.
Configuration software will read this register to determine where
the 256-MB range of addresses resides for this particular host
bridge.
The address used to access the PCI Express configuration space
for a specific device can be determined as follows:
PCI Express Base Address + Bus Number * 1 MB + Device
Number * 32 KB + Function Number * 4 KB
The address used to access the PCI Express configuration space
for Device 1 in this component would be as follows.
PCI Express Base Address + 0 * 1 MB + 1 * 32 KB + 0 * 4 KB =
PCI Express Base Address + 32 KB.
Note: This address is at the beginning of the 4-KB space that
contains both the PCI compatible configuration space and the
PCI Express extended configuration space.
0/0/0/PCI
48-4Bh
E0000000h
R/W/L; RO
32 bits
(Sheet 1 of 2)
Host Bridge Device 0 - Configuration Registers (D0:F0)
Description
Datasheet