QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 119

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6.2.5
:
6.2.6
Datasheet
C0DRB0 - Channel 0 DRAM Rank Boundary 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The DRAM rank boundary register defines the upper boundary address of each DRAM
rank with a granularity of 128 MB (256 Mbit, x16 devices). Each rank has its own
single-byte DRB register. These registers are used to determine which chip select will
be active for a given address.
Channel and Rank Map:
In all modes, if a DIMM is single sided, it appears as a populated rank and an empty
rank. A DRB must be programmed appropriately for each.
Each rank is represented by a byte. Each byte has the following format:
C0DRB1 - Channel 0 DRAM Rank Boundary 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DRB0.
104h to 107h
7:0
Bit
ch0 rank1:
ch0 rank2:
ch1 rank0:
ch1 rank1:
ch0 rank0
ch0 rank3
Access
R/W
Default
Value
Reserved
00h
100h
101h
102h
103h
180h
181h
Channel 0 DRAM Rank Boundary Address:
This 8-bit value defines the upper and lower addresses for
each DRAM rank. Bits 6:2 are compared against Address 31:27
to determine the upper address limit of a particular rank. Bits
1:0 must be 0’s. Bit 7 may be programmed to a 1 in the
highest DRB (DRB3) if 4 GBs of memory is present.
0/0/0/MCHBAR
100h
00h
R/W
8 bits
0/0/0/MCHBAR
101h
00h
R/W
8 bits
Description
119