QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 108

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

5.1.31
108
ERRCMD - Error Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the MCH responses to various system errors. Since the MCH does
not have an SERRB signal, SERR messages are passed from the MCH to the ICH over
DMI. When a bit in this register is set, a SERR message will be generated on DMI
whenever the corresponding flag is set in the ERRSTS register. The actual generation of
the SERR message is globally enabled for Device 0 via the PCI Command register.
8
7
6:0
15:13
Bit
12
11
10
9
R/W
R/W
RO
Access
R/W
R/W
RO
RO
RO
0b
0b
00h
Default
Value
000b
0b
0b
0b
0b
Reserved
Reserved
SERR on (G)MCH Thermal Sensor Event (TSESERR):
1: The MCH generates a SERR DMI special cycle when bit 11 of
the ERRSTS is set. The SERR must not be enabled at the same
time as the SMI for the same thermal sensor event.
0: Reporting of this condition via SERR messaging is disabled.
Reserved
SERR on LOCK to non-DRAM Memory (LCKERR):
1: The MCH will generate a DMI SERR special cycle whenever a
CPU lock cycle is detected that does not hit DRAM.
0: Reporting of this condition via SERR messaging is disabled.
SERR on DRAM Refresh Timeout (DRTOERR):
1: The (G)MCH generates an SERR DMI special cycle when a
DRAM Refresh timeout occurs.
0: Reporting of this condition via SERR messaging is disabled.
SERR on DRAM Throttle Condition (DTCERR):
1: The (G)MCH generates an SERR DMI special cycle when a
DRAM Read or Write Throttle condition occurs.
0: Reporting of this condition via SERR messaging is disabled.
Reserved
0/0/0/PCI
CA-CBh
0000h
R/W; RO
16 bits
Host Bridge Device 0 - Configuration Registers (D0:F0)
Description
Datasheet