QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 85

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Host Bridge Device 0 - Configuration Registers (D0:F0)
5.1.6
5.1.7
Datasheet
CC - Class Code
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register identifies the basic function of the device, a more specific sub-class, and a
register-specific programming interface.
MLT - Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Device 0 in the MCH is not a PCI master. Therefore this register is not implemented.
23:16
15:8
7:0
Bit
7:0
Bit
Access
Access
RO
RO
RO
RO
Default
Default
Value
Value
06h
00h
00h
00h
Base Class Code (BCC):
This is an 8-bit value that indicates the base class code for the
MCH. This code has the value 06h, indicating a bridge device.
Sub-Class Code (SUBCC):
This is an 8-bit value that indicates the category of bridge into
which the MCH falls. The code is 00h indicating a host bridge.
Programming Interface (PI):
This is an 8-bit value that indicates the programming interface
of this device. This value does not specify a particular register
set layout and provides no practical use for this device.
Reserved
0/0/0/PCI
09-0Bh
060000h
RO
24 bits
0/0/0/PCI
0Dh
00h
RO
8 bits
Description
Description
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