QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 242

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

242
Bit
2
1
0
Access
R/W
R/W
R/W
Default
Value
0b
0b
0b
ISA Enable (ISAEN):
Needed to exclude legacy resource decode to route ISA resources
to legacy decode path. Modifies the response by the (G)MCH to
an I/O access issued by the CPU that target ISA I/O addresses.
This applies only to I/O addresses that are enabled by the
IOBASE and IOLIMIT registers.
I/O transactions will be mapped to PCI Express-G*.
transactions addressing the last 768 bytes in each 1-KB block
even if the addresses are within the range defined by the IOBASE
and IOLIMIT registers. Instead of going to PCI Express-G these
cycles will be forwarded to DMI where they can be subtractively
or positively claimed by the ISA bridge.
SERR Enable (SERREN):
primary side that could result in an SERR.
result in SERR message when individually enabled by the Root
Control register.
Parity Error Response Enable (PEREN):
Controls whether or not the Master Data Parity Error bit in the
Secondary Status register is set when the MCH receives across
the link (upstream) a Read Data Completion Poisoned TLP
cannot be set.
can be set.
0: All addresses defined by the IOBASE and IOLIMIT for CPU
1: (G)MCH will not forward to PCI Express-G any I/O
0: No forwarding of error messages from secondary side to
1: ERR_COR, ERR_NONFATAL, and ERR_FATAL messages
0: Master Data Parity Error bit in Secondary Status register
1: Master Data Parity Error bit in Secondary Status register
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
(Sheet 2 of 2)
Description
Datasheet