QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 75

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

(G)MCH Configuration Process and Registers
4.3
4.4
Datasheet
(G)MCH Register Introduction
The (G)MCH contains two sets of software accessible registers, accessed via the host
CPU I/O address space: Control registers and internal configuration registers.
The (G)MCH internal registers (I/O Mapped, Configuration and PCI Express Extended
Configuration registers) are accessible by the host CPU. The registers that reside within
the lower 256 bytes of each device can be accessed as byte, word (16-bit), or dword
(32-bit) quantities, with the exception of CONFIG_ADDRESS, which can only be
accessed as a dword. All multi-byte numeric fields use “little-endian” ordering (i.e.,
lower addresses contain the least significant parts of the field). Registers which reside
in bytes 256 through 4095 of each device may only be accessed using memory mapped
transactions in dword (32-bit) quantities.
Some of the (G)MCH registers described in this section contain reserved bits. These
bits are labeled Reserved. Software must deal correctly with fields that are reserved.
On reads, software must use appropriate masks to extract the defined bits and not rely
on reserved bits being any particular value. On writes, software must ensure that the
values of reserved bit positions are preserved. That is, the values of reserved bit
positions must first be read, merged with the new values for other bit positions and
then written back. Note the software does not need to perform read, merge, and write
operation for the configuration address register.
In addition to reserved bits within a register, the (G)MCH contains address locations in
the configuration space of the host bridge entity that are marked either “Reserved” or
“Intel Reserved”. The (G)MCH responds to accesses to “Reserved” address locations by
completing the host cycle. When a Reserved register location is read, a 0 value is
returned. (Reserved registers can be 8, 16, or 32 bits in size). Writes to Reserved
registers have no effect on the (G)MCH. Registers that are marked as Intel Reserved
must not be modified by system software. Writes to Intel Reserved registers may cause
system failure. Reads from Intel Reserved registers may return a non-zero value.
Upon a Full Reset, the (G)MCH sets its entire set configuration registers to
predetermined default states. Some register values at reset are determined by external
strapping options. The default state represents the minimum functionality feature set
required to successfully bringing up the system. Hence, it does not represent the
optimal system configuration. It is the responsibility of the system initialization
software (usually BIOS) to properly determine the DRAM configurations, operating
parameters and optional system features that are applicable, and to program the
(G)MCH registers accordingly.
I/O Mapped Registers
The (G)MCH contains two registers that reside in the CPU I/O address space − the
Configuration Address (CONFIG_ADDRESS) register and the Configuration Data
(CONFIG_DATA) register. The Configuration Address register enables/disables the
configuration space and determines what portion of configuration space is visible
through the Configuration Data window.
1. Control registers are I/O mapped into the CPU I/O space, which control access to
2. Internal configuration registers residing within the (G)MCH are partitioned into four
PCI and PCI Express configuration space (see section entitled I/O Mapped
registers).
logical device register sets (“logical” since they reside within a single physical
device). The first register set is dedicated to host bridge functionality (i.e., DRAM
configuration, other chipset operating parameters and optional features). The
second register block is dedicated to host-PCI Express bridge functions (controls
PCI Express interface configurations and operating parameters). The third register
block is for the internal graphics functions.
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