QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 316

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

8.2.27
8.3
8.4
Table 14.
316
MMIO Address Register
MMIO Data Register
Register Name
ASLS - ASL Storage
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This software scratch register only needs to be read/write accessible. The exact bit
register usage must be worked out in common between System BIOS and driver
software, but storage for switching/indicating up to 6 devices is possible with this
amount. For each device, the ASL control method with require two bits for _DOD (BIOS
detectable yes or no, VGA/NonVGA), one bit for _DGS (enable/disable requested), and
two bits for _DCS (enabled now/disabled now, connected or not).
Device 2 – PCI I/O Registers
The following are not PCI configuration registers; they are I/O registers. This
mechanism allows access to internal graphics MMIO registers must not be used to
access VGA IO registers which are mapped through the MMIO space. VGA registers
must be accessed directly through the dedicated VGA IO ports.
Device 2 I/O Configuration Registers
MMIO Configuration Registers Summary Table
31:0
Bit
Access
R/W
Index
Data
00000000h
Register
Symbol
Default
Value
R/W according to a software controlled usage to support device
switching
IOBAR + 0
IOBAR + 4
Register
Internal Graphics Device 2 Configuration Register (D2:F0-F1)
Start
0/2/1/PCI
FC-FFh
00000000h
R/W
32 bits
IOBAR + 3
IOBAR + 7
Register End
Description
00000000h
00000000h
Default
Value
R/W
R/W
Access
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