QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 241

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

PCI Express Graphics Device 1 Configuration Registers (D1:F0)
7.1.22
Datasheet
BCTRL1 - Bridge Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register provides extensions to the PCICMD1 register that are specific to PCI-to-
PCI bridges. The BCTRL provides additional control for the secondary interface (i.e., PCI
Express-G) as well as some bits that affect the overall behavior of the “virtual” host-PCI
Express bridge embedded within (G)MCH, e.g., VGA compatible address ranges
mapping.
15:12
Bit
11
10
9
8
7
6
5
4
3
Access
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
Default
Value
0h
0b
0b
0b
0b
0b
0b
0b
0b
0b
Reserved
Discard Timer SERR Enable (DTSERRE):
Not Applicable or Implemented. Hardwired to 0.
Discard Timer Status (DTSTS):
Not Applicable or Implemented. Hardwired to 0.
Secondary Discard Timer (SDT):
Not Applicable or Implemented. Hardwired to 0.
Primary Discard Timer (PDT):
Not Applicable or Implemented. Hardwired to 0.
Fast Back-to-Back Enable (FB2BEN):
Not Applicable or Implemented. Hardwired to 0.
Secondary Bus Reset (SRESET):
Setting this bit triggers a hot reset on the corresponding PCI
Express* Port. This will force the LTSSM to transition to the Hot
Reset state (via Recovery) from L0, L0s, or L1 states.
Master Abort Mode (MAMODE):
When acting as a master, unclaimed reads that experience a
master abort returns all 1's and any writes that experience a
master abort completes normally and the data is thrown away.
Hardwired to 0.
VGA 16-bit Decode (VGA16D):
Enables the PCI-to-PCI bridge to provide 16-bit decoding of VGA
I/O address precluding the decoding of alias addresses every
1 KB. This bit only has meaning if bit 3 (VGA Enable) of this
register is also set to 1, enabling VGA I/O decoding and
forwarding by the bridge.
VGA Enable (VGAEN):
Controls the routing of CPU initiated transactions targeting VGA
compatible I/O and memory address ranges. See the VGAEN/
MDAP table in Device 0, offset 97h[0].
0: Execute 10-bit address decodes on VGA I/O accesses.
1: Execute 16-bit address decodes on VGA I/O accesses.
0/1/0/PCI
3E-3Fh
0000h
R/W; RO
16 bits
(Sheet 1 of 2)
Description
241