QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 135

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6.2.17
Datasheet
C0DRC1 - Channel 0 DRAM Controller Mode 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:20
19:16
15:13
1:0
Bit
Bit
12
11
3
2
Access
Access
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
Default
Value
Default
Value
0000h
10b
000b
0b
0b
0b
0b
0
Reserved
Burst Length (BL):
The burst length is the number of QWORDS returned by a DIMM
per read command, when not interrupted. This bit is used to
select the DRAM controller's Burst Length Operation mode. It
must be set to match to the behavior of the DIMM.
0: Reserved
1: Burst Length of 8
DRAM Type (DT):
Used to select between supported SDRAM types.
10: Second Revision Dual Data Rate (DDR2) SDRAM
Other: Reserved
Reserved
CKE Tri-state Enable Per Rank:
Bit 19 corresponds to rank 3
Bit 18 corresponds to rank 2
Bit 16 corresponds to rank 0
Bit 17 corresponds to rank 1
0 = CKE is not tri-stated.
1 = CKE is tri-stated. This is set only if the rank is physically not
populated.
Reserved
CS# Tri-state Enable:
When set to a 1, the DRAM controller will tri-state CS# when the
corresponding CKE is deasserted.
0: Address Tri-state Disabled
1: Address Tri-state Enabled
Address Tri-state Enable:
and CS# (CS# if lines only when all CKEs are deasserted. CKEs
deassert based on Idle timer or max rank count control.)
0: Address Tri-state Disabled
1: Address Tri-state Enabled
When set to a 1, the DRAM controller will tri-state the MA, CMD,
0/0/0/MCHBAR
124-127h
00000000h
R/W; RO
32 bits
(Sheet 4 of 4)
Description
Description
135