QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 9

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Datasheet
7.2
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10 SBUSN1 - Secondary Bus Number .......................................................... 234
7.1.11 SUBUSN1 - Subordinate Bus Number ...................................................... 234
7.1.12 IOBASE1 - I/O Base Address.................................................................. 235
7.1.13 IOLIMIT1 - I/O Limit Address ................................................................. 235
7.1.14 SSTS1 - Secondary Status..................................................................... 236
7.1.15 MBASE1 - Memory Base Address ............................................................ 237
7.1.16 MLIMIT1 - Memory Limit Address ........................................................... 237
7.1.17 PMBASE1 - Prefetchable Memory Base Address ........................................ 238
7.1.18 PMLIMIT1 - Prefetchable Memory Limit Address........................................ 239
7.1.19 CAPPTR1 - Capabilities Pointer ............................................................... 239
7.1.20 INTRLINE1 - Interrupt Line .................................................................... 240
7.1.21 INTRPIN1 - Interrupt Pin ....................................................................... 240
7.1.22 BCTRL1 - Bridge Control........................................................................ 241
7.1.23 PM_CAPID1 - Power Management Capabilities .......................................... 243
7.1.24 PM_CS1 - Power Management Control/Status........................................... 244
7.1.25 SS_CAPID - Subsystem ID and Vendor ID Capabilities............................... 246
7.1.26 SS - Subsystem ID and Subsystem Vendor ID.......................................... 246
7.1.27 MSI_CAPID - Message Signaled Interrupts Capability ID ............................ 247
7.1.28 MC - Message Control ........................................................................... 247
7.1.29 MA - Message Address .......................................................................... 248
7.1.30 MD - Message Data .............................................................................. 249
7.1.31 PEG_CAPL - PCI Express-G Capability List................................................ 249
7.1.32 PEG_CAP - PCI Express-G Capabilities ..................................................... 250
7.1.33 DCAP - Device Capabilities..................................................................... 251
7.1.34 DCTL - Device Control........................................................................... 252
7.1.35 DSTS - Device Status............................................................................ 253
7.1.36 LCAP - Link Capabilities......................................................................... 254
7.1.37 LCTL - Link Control ............................................................................... 255
7.1.38 LSTS - Link Status................................................................................ 256
7.1.39 SLOTCAP - Slot Capabilities ................................................................... 257
7.1.40 SLOTCTL - Slot Control ......................................................................... 258
7.1.41 SLOTSTS - Slot Status .......................................................................... 259
7.1.42 RCTL - Root Control.............................................................................. 260
7.1.43 RSTS - Root Status............................................................................... 261
7.1.44 PEGLC - PCI Express-G Legacy Control .................................................... 262
7.1.45 PEGCTL1 – PEG Control 1 ...................................................................... 262
7.1.46 PEGTCFG – PEG Timing Configuration ..................................................... 262
PCI Express Device 1 Extended Configuration Registers ........................................ 263
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
VID1 - Vendor Identification .................................................................. 227
DID1 - Device Identification................................................................... 228
PCICMD1 - PCI Command...................................................................... 228
PCISTS1 - PCI Status............................................................................ 230
RID1 - Revision Identification................................................................. 231
CC1 - Class Code ................................................................................. 232
CL1 - Cache Line Size ........................................................................... 232
HDR1 - Header Type ............................................................................. 233
PBUSN1 - Primary Bus Number .............................................................. 233
VCECH - Virtual Channel Enhanced Capability Header................................ 264
PVCCAP1 - Port VC Capability Register 1.................................................. 264
PVCCAP2 - Port VC Capability Register 2.................................................. 265
PVCCTL - Port VC Control ...................................................................... 265
VC0RCAP - VC0 Resource Capability........................................................ 266
VC0RCTL - VC0 Resource Control ........................................................... 266
VC0RSTS - VC0 Resource Status ............................................................ 267
RCLDECH - Root Complex Link Declaration Enhanced ................................ 267
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