QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 319

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

System Address Map
9
Note:
Datasheet
System Address Map
The Mobile Intel 945GM/GME/PM and Intel 945GT Express Chipsets support up to 4 GB
of addressable memory space and 64 KB+3 of addressable I/O space. There is a
programmable memory address space under the 1-MB region which is divided into
regions which can be individually controlled with programmable attributes such as
Disable, Read/Write, Write Only, or Read Only. Attribute programming is described in
Chapter
separate memory regions are used for. I/O address space has simpler mapping and is
explained in
Addressing of memory ranges larger than 4 GB is not supported. The HREQ [4:3] FSB
pins are decoded to determine whether the access is above or below 4 GB.
The Mobile Intel 945GM/GME/PM and Intel 945GT Express Chipsets are capable of
supporting up to 4 GB of physical memory. All other variants, except Ultra Mobile
945GU Express Chipset, support only up to 2 GB of physical memory. The Ultra Mobile
945GU Express Chipset supports up to 1 GB.
The (G)MCH does not support the PCI dual address cycle (DAC) mechanism, PCI
Express 64-bit prefetchable memory transactions, or any other addressing mechanism
that allows addressing of greater than 4 GB on either the DMI or PCI Express interface.
The (G)MCH does not limit DRAM space in hardware. There is no hardware lock to stop
someone from inserting more memory than is addressable.
In the following sections, it is assumed that all of the compatibility memory ranges
reside on the DMI. The exception to this rule is VGA ranges, which may be mapped to
PCI Express, DMI, or to the internal graphics device (IGD). In the absence of more
specific references, cycle descriptions referencing PCI should be interpreted as the
DMI/PCI, while cycle descriptions referencing PCI Express or IGD are related to the PCI
Express bus or the internal graphics device respectively. The (G)MCH does not remap
APIC or any other memory spaces above TOLUD (Top of Low Usable DRAM). The TOLUD
register is set to the appropriate value by BIOS.
The Address Map includes a number of programmable ranges:
1. Device 0:
A. EPBAR – Egress port registers. Necessary for setting up VC1 as an isochronous
channel using time based weighted round robin arbitration. (4-KB window)
B. MCHBAR – Memory mapped range for internal (G)MCH registers. For example,
memory buffer register controls. (16-KB window)
C. PCIEXBAR – Flat memory-mapped address spaced to access device configuration
registers. This mechanism can be used to access PCI configuration space (0-FFFh) and
Extended configuration space (100h-FFFh) for PCI Express devices. This enhanced
configuration access mechanism is defined in the PCI Express* Base Specification. (64-
MB, 128-MB, or 256-MB window).
D. DMIBAR –This window is used to access registers associated within the MCH/ICH
(DMI) register memory range. (4-KB window)
E. GGC – (G)MCH graphics control register. Used to select the amount of main memory
that is pre-allocated to support the internal graphics device in VGA (non-linear) and
Native (linear) modes. (0-MB to 64-MB options).
5. This section focuses on how the memory space is partitioned and what the
Section
9.9.
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