QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 147

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6.2.41
Datasheet
C1DTPEW - Channel 1 DRAM Rank Throttling Passive
Event Weights
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register contains programmable Event weights that are input into the averaging
filter. Each Event weight is a normalized 8-bit value that the BIOS must program. The
BIOS must account for burst length considerations. It is also possible for BIOS to take
into account loading variations caused by different memory types and population of
ranks. All bits in this register can be locked by the DTLOCK bit in the C0DTC register.
63:48
47:40
39:32
31:24
23:16
15:8
7:0
Bit
Access
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
RO
Default
Value
0000h
00h
00h
00h
00h
00h
00h
Reserved
Additive Weight for ODT:
This value is added to the total weight of a rank if ODT on that
rank is asserted. Note that this value should reflect whether the
DRAM modules have been programmed for 75- or 150-Ω
termination.
Weight for Any Open Page during Active (WAOPDA):
This value is input to the filter if, during the present clock, the
corresponding rank has any pages open and is not in power
down. The value programmed here is IDD3N from the JEDEC.
All Banks Precharge Active (ABPA):
This value is input to the filter if, during the present clock, the
corresponding rank has all banks precharged but is not in power
down. The value programmed here is IDD2N from the JEDEC
spec.
Weight for Any Open Page during Power Down
(WAOPDPD):
This value is input to the filter if, during the present clock, the
corresponding rank is in power down with pages open. The value
programmed here is IDD3P from the JEDEC.
All Banks Precharge Power Down (ABPPD):
This value is input to the filter if, during the present clock, the
corresponding rank has all banks precharged and is powered
down. The value programmed here is IDD2P from the JEDEC
spec.
Self Refresh:
This value is input to the filter if in a clock the corresponding
rank is in self refresh.
0/0/0/MCHBAR
1C8-1CFh
0000000000000000h
R/W/L; RO
64 bits
Description
147