QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 376

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

10.5.4.1
Table 38.
10.5.4.1.1
10.5.4.1.2
10.5.4.2
376
Analog Display Port Characteristics
The analog display port provides a RGB signal output along with a HSYNC and VSYNC
signal. There is an associated DDC signal pair that is implemented using GPIO pins
dedicated to the analog port. The intended target device is for a CRT based monitor
with a VGA connector. Display devices such as LCD panels with analog inputs may work
satisfactory but no functionality has been added to the signals to enhance that
capability.
Analog Port Characteristics
Integrated RAMDAC
The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that
transforms the digital data from the graphics and video subsystems to analog data for
the CRT monitor. (G)MCH’s integrated 400 MHz RAMDAC supports resolutions up to
2048 x 1536. Three 8-bit DACs provide the R, G, and B signals to the monitor.
Sync Signals
HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector.
Since these levels cannot be generated internal to the device, external level shifting
buffers are required. These signals can be polarity adjusted and individually disabled in
one of the two possible states. The sync signals should power up disabled in the high
state. No composite sync or special flat panel sync support will be included.
Dedicated LFP LVDS Port
The display pipe selected by the LVDS display port is programmed with the panel timing
parameters that are determined by installed panel specifications or read from an
onboard EDID ROM. The programmed timing values are then “locked” into the registers
to prevent unwanted corruption of the values. From that point on, the display modes
are changed by selecting a different source size for that pipe, programming the VGA
registers, or selecting a source size and enabling the VGA. The timing signals will
remain stable and active through mode changes. These mode changes include VGA to
VGA, VGA to HiRes, HiRes to VGA, and HiRes to HiRes.
The transmitter can operate in a variety of modes and supports several data formats.
The serializer supports 6-bit color and Single- or Dual-channel operating modes. The
display stream from the display pipe is sent to the LVDS transmitter port at the dot
HSYNC
Signal
VSYNC
DDC
RGB
Voltage Range
Monitor Sense
Analog Copy Protection
Sync on Green
Voltage
Enable/Disable
Polarity adjust
Composite Sync Support
Special Flat Panel Sync
Stereo Sync
Voltage
Control
Port Characteristic
Externally buffered to 5V
Through GPIO interface
VGA or port control
Analog Compare
0.7 V p-p only
Port control
Support
2.5 V
No
No
No
No
No
Functional Description
Datasheet