QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 133

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
Datasheet
23:16
13:12
10:8
Bit
15
14
11
7
Access
R/W
R/W
R/W
R/W
R/W
RO
RO
Default
Value
000h
000b
00b
0b
0b
1b
0b
Reserved
CMD Pin Dual Copy Enable:
In a Single-channel mode, the CMD pins (MA, BS, RAS, CAS, WE)
on both channels are driven and are physical copies of each other.
Setting this bit enables the CMD pins on channel B. Having the
additional copy of CMD pins helps reduce loading on these pins,
since in a two DIMM system, each copy can be hooked up to one
DIMM. In a single DIMM system, the second copy can be disabled
to eliminate unnecessary toggling of these pins.
If this bit needs to be set, BIOS should do that before memory
initialization sequence.
This bit should not be set in a dual-channel system.
Reserved
Reserved
Reserved
Refresh Mode Select (RMS):
This field determines whether refresh is enabled and, if so, at
what rate refreshes will be executed.
000 to 001: Reserved
010: Refresh enabled. Refresh interval 7.8 µs
Other: Reserved
Reserved
(Sheet 2 of 4)
Description
133