QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 320

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

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Device 1, Function 0:
MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window.
PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window.
IOBASE1/IOLIMIT1 – PCI Express port IO access window.
Device 2, Function 0:
MMADR – IGD registers and internal graphics instruction port. (512-KB window)
IOBAR – I/O access window for internal graphics. Through this window address/data
register pair, using I/O semantics, the IGD and internal graphics instruction port
registers can be accessed. Note this allows accessing the same registers as MMADR. In
addition, the IOBAR can be used to issue writes to the GTTADR table.
GMADR – Internal graphics translation window. (256-MB window)
GTTADR – Internal graphics translation table location. (256-KB window).
Device 2, Function 1:
MMADR – Function 1 IGD registers and internal graphics instruction port. (512-KB
window)
The rules for the above programmable ranges are:
Figure 10
1. ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or
2. In the case of overlapping ranges with memory, the memory decode will be given
3. There are no Hardware Interlocks to prevent problems in the case of overlapping
4. Accesses to overlapped ranges may produce indeterminate results.
5. The only peer-to-peer cycles allowed below the top of memory (register TOLUD)
system designers responsibility to limit memory population so that
adequate PCI, PCI Express, High BIOS, PCI Express Memory Mapped
space, and APIC memory space can be allocated.
priority.
ranges.
are DMI to PCI Express VGA range writes. Note that peer to peer cycles to the
Internal Graphics VGA range are not supported.
represents system memory address map in a simplified form.
System Address Map
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