QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 76

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

4.4.1
76
CONFIG_ADDRESS—Configuration Address Register
I/O Address:
Size:
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DW. A byte or
word reference will “pass through” the Configuration Address register and DMI onto the
PCI_A bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number,
Device Number, Function Number, and Register Number for which a subsequent
configuration access is intended.
30:24
23:16
15:11
Bit
31
Access &
Default
R/W
R/W
R/W
00h
00h
00h
RO
0b
Configuration Enable (CFGE):
When this bit is set to 1, accesses to PCI configuration space are enabled.
If this bit is reset to 0, accesses to PCI configuration space are disabled.
Reserved
Bus Number:
If the Bus Number is programmed to 00h the target of the Configuration
Cycle is a PCI Bus 0 agent. If this is the case and the (G)MCH is not the
target (i.e., the device number is >= 3 and not equal to 7), then a DMI
Type 0 Configuration Cycle is generated.
If the Bus Number is non-zero, and does not fall within the ranges
enumerated by Device 1’s SECONDARY BUS NUMBER or SUBORDINATE
BUS NUMBER register, then a DMI Type 1 Configuration Cycle is
generated.
If the Bus Number is non-zero and matches the value programmed into
the SECONDARY BUS NUMBER register of Device 1, a Type 0 PCI
Configuration Cycle will be generated on PCI Express-G*.
If the Bus Number is non-zero, greater than the value in the SECONDARY
BUS NUMBER register of Device 1 and less than or equal to the value
programmed into the SUBORDINATE BUS NUMBER register of Device 1 a
Type 1 PCI Configuration Cycle will be generated on PCI Express-G.
This field is mapped to byte 8 [7:0] of the request header format during
PCI Express Configuration cycles and A[23:16] during the DMI Type 1
Configuration Cycles.
Device Number:
This field selects one agent on the PCI bus selected by the Bus Number.
When the Bus Number field is “00” the (G)MCH decodes the Device
Number field. The (G)MCH is always Device Number 0 for the host bridge
entity, Device Number 1 for the host-PCI Express entity. Therefore, when
the Bus Number =0 and the Device Number equals 0,1, 2 or 7 the
internal (G)MCH devices are selected.
This field is mapped to byte 6 [7:3] of the request header format during
PCI Express and DMI Configuration Cycles.
0CF8h Accessed as a DW
32 bits
(Sheet 1 of 2)
Description
(G)MCH Configuration Process and Registers
Datasheet