QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 302

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

8.2.4
302
PCISTS2 - PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
PCISTS is a 16-bit status register that reports the occurrence of a PCI-compliant
master abort and PCI-compliant target abort. PCISTS also indicates the DEVSEL#
timing that has been set by the IGD.
10:9
2:0
Bit
15
14
13
12
11
8
7
6
5
4
3
Access
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
00b
0b
0b
0b
0b
0b
0b
1b
0b
0b
1b
0b
0h
Detected Parity Error (DPE):
Since the IGD does not detect parity, this bit is always hardwired
to 0.
Signaled System Error (SSE):
The IGD never asserts SERR#, therefore this bit is hardwired to
0.
Received Master Abort Status (RMAS):
The IGD never gets a Master Abort, therefore this bit is hardwired
to 0.
Received Target Abort Status (RTAS):
The IGD never gets a Target Abort, therefore this bit is hardwired
to 0.
Signaled Target Abort Status (STAS):
Hardwired to 0. The IGD does not use target abort semantics.
DEVSEL Timing (DEVT):
Not applicable. These bits are hardwired to 00.
Master Data Parity Error Detected (DPD):
Since Parity Error Response is hardwired to disabled (and the IGD
does not do any parity detection), this bit is hardwired to 0.
Fast Back-to-Back (FB2B):
Hardwired to 1. The IGD accepts fast back-to-back when the
transactions are not to the same agent.
User Defined Format (UDF):
Hardwired to 0.
66-MHz PCI Capable (66C):
Not applicable. Hardwired to 0.
Capability List (CLIST):
This bit is set to 1 to indicate that the register at 34h provides an
offset into the function's PCI Configuration Space containing a
pointer to the location of the first item in the list.
Interrupt Status:
Hardwired to 0.
Reserved
Internal Graphics Device 2 Configuration Register (D2:F0-F1)
0/2/1/PCI
6-7h
0090h
RO
16 bits
Description
Datasheet