QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 136

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

6.2.18
136
C0DRC2 - Channel 0 DRAM Controller Mode 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:28
27:24
23:13
11:9
10:9
7:0
8:2
1:0
Bit
Bit
12
8
Access
Access
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
Default
Default
Value
000h
000b
Value
00b
00h
00b
0h
0b
00b
00h
1b
Reserved
Dram ODT Tristate Enable Per Rank:
Bit 27 corresponds to rank 3
Bit 26 corresponds to rank 2
Bit 24 corresponds to rank 0
Bit 25 corresponds to rank 1
0 = ODT is not tri-stated.
1 = ODT is tri-stated. This is set only if the rank is physically not
populated.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DRAM Channel IO-Buffers Activate:
This bit is cleared to 0 during reset and remains inactive until it
is set to 1 by BIOS.
While 0, the DRAM controller core logic forces the state of the
IO-buffers in this channel to “reset” or “preset”, depending on
the specific buffer type.
While 1, the DRAM controller core logic enables the DRAM IO-
buffers in this channel to operate normally.
Reserved
0/0/0/MCHBAR
128-12Bh
00000000h
R/W; RO
32 bits
Description
Description
Device 0 Memory Mapped I/O Register
Datasheet