QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 341
QG82945GSE S LB2R
Manufacturer Part Number
QG82945GSE S LB2R
Description
GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
Manufacturer
Intel
Datasheet
1.AU80586GE025DSLB73.pdf
(482 pages)
- Current page: 341 of 482
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Functional Description
10.2.3.2
Table 25.
Figure 15.
Datasheet
Dual-channel Asymmetric Mode
This mode trades performance for system design flexibility. Unlike the previous mode,
addresses start in channel A and stay there until the end of the highest rank in channel
A, then addresses continue from the bottom of channel B to the top. Real world
applications are unlikely to make requests that alternate between addresses that sit on
opposite channels with this memory organization, so in most cases, bandwidth will be
limited to that of a single channel. The system designer is free to populate or not to
populate any rank on either channel, including either degenerate single-channel case.
Sample System Memory Organization with Asymmetric Channels
System Memory Styles
Rank 1
Rank 0
Population
Channel A
1024 MB
512 MB
Channel A
DRBs in
1536 MB
512 MB
Population
Channel B
512 MB
256 MB
Channel B
DRBs in
768 MB
256 MB
341
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