QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 298

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

8.1.36
8.2
Table 13.
298
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Class Code Register
Cache Line Size
Master Latency Timer
Header Type
Reserved
Memory Mapped Range Address
Subsystem Vendor Identification
Subsystem Identification
Video BIOS ROM Base Address
Capabilities Pointer
Minimum Grant
Register Name
ASLS - ASL Storage
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This SW scratch register only needs to be read/write accessible. The exact bit register
usage must be worked out in common between System BIOS and driver software, but
storage for switching/indicating up to 6 devices is possible with this amount. For each
device, the ASL control method with require two bits for _DOD (BIOS detectable yes or
no, VGA/NonVGA), one bit for _DGS (enable/disable requested), and two bits for _DCS
(enabled now/disabled now, connected or not).
Device 2 Function 1 PCI Configuration Registers
Device 2 Function 1 PCI Configuration Registers Summary Table (Sheet 1 of 2)
31:0
Bit
Access
R/W
00000000h
Default
Value
VID2
DID2
PCICMD2
PCISTS2
RID2
CC
CLS
MLT2
HDR2
MMADR
SVID2
SID2
ROMADR
CAPPOINT
MINGNT
Register Symbol
device switching
RW according to a software controlled usage to support
Internal Graphics Device 2 Configuration Register (D2:F0-F1)
0/2/0/PCI
FC-FFh
00000000h
R/W
32 bits
0
2
4
6
8
9
C
D
E
F
2C
2E
34
3E
10
30
Register
Start
1
3
5
7
8
B
C
D
E
F
2D
2F
34
3E
13
33
Register
Description
End
8086h
27A6h
0090h
00h
038000h
00h
00h
80h
0000h
0000h
D0h
00h
0000h
00000000h
00000000h
Default
Value
RO
RO
R/W; RO
RO
RO
RO
RO
RO
RO
R/W; RO
RO
RO
RO
RO
RO
Access
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