QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 72

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Figure 6.
4.2.4
72
3
1
1
3
1
served
DMI Type 1 Configuration Address Translation
PCI Express Enhanced Configuration Mechanism
PCI Express extends the configuration space to 4096 bytes per device/function as
compared to 256 bytes allowed by the PCI Local Bus Specification. PCI Express
configuration space is divided into a conventional PCI 2.3-compatible region, which
consists of the first 256 bytes of a logical device’s configuration space and a PCI
Express extended region, which consists of the remaining configuration space.
The PCI-compatible region can be accessed using either the mechanism defined in the
previous section or using the enhanced PCI Express configuration access mechanism
described in this section. The extended configuration registers may only be accessed
using the enhanced PCI Express configuration access mechanism. To maintain
compatibility with PCI configuration addressing mechanisms, system software must
access the extended configuration space using 32-bit operations (32-bit aligned) only.
These 32-bit operations include byte enables allowing only appropriate bytes within the
dword to be accessed. Locked transactions to the PCI Express memory mapped
configuration address space are not supported. All changes made using either access
mechanism are equivalent.
The enhanced PCI Express configuration access mechanism utilizes a flat memory-
mapped address space to access device configuration registers. This address space is
reported by the system firmware to the operating system. PCIEXBAR defines the base
address for a 64-, 128-, or 256-MB block of addresses below the top of addressable
memory (currently 4 GB) for the configuration space associated with all devices and
functions that are potentially a part of the PCI Express root complex hierarchy. The PCI
Express Configuration Transaction Header includes an additional 4 bits (Extended
Register Address[3:0]) between the function number and register address fields to
provide indexing into the 4 KB of configuration space allocated to each potential device.
For PCI Compatible Configuration Requests, the Extended Register Address field must
be all 0’s.
Re-
Reserved
2
8
2
8
2
7
2
7
0
DMI TYPE 1 CONFIGURATION ADDRESS EXTENSION
2
4
2
4
2
3
2
3
Bus Number
Bus Number
CONFIG_ADDRESS
1
6
1
6
1
5
1
5
Number
Number
Device
Device
(G)MCH Configuration Process and Registers
1
1
1
1
1
0
1
0
Func-
Func-
tion
tion
8 7
8 7
Register Number x x
Register Number 0 1
2 1 0
2 1 0
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