QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 82

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

82
15:10
9:9
8:8
7:7
6:6
5:5
4:4
3:3
2:2
1:1
0:0
Bit
Access
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
00h
0b
0b
0b
0b
0b
0b
0b
1b
1b
0b
Reserved
Fast Back-to-Back Enable (FB2B):
This bit controls whether or not the master can do fast back-to-
back write. Since Device 0 is strictly a target this bit is not
implemented and is hardwired to 0. Writes to this bit position
have no affect.
SERR Enable (SERRE):
This bit is a global enable bit for Device 0 SERR messaging. The
(G)MCH does not have an SERR signal. The (G)MCH
communicates the SERR condition by sending an SERR
message over (G)MCH ICH Serial Interface (DMI) to the ICH.
If this bit is set to a 1, the (G)MCH is enabled to generate SERR
messages over DMI for specific Device 0 error conditions that
are individually enabled in the ERRCMD register. The error
status is reported in the ERRSTS and PCISTS registers.
If SERRE is clear, then the SERR message is not generated by
the (G)MCH for Device 0. Note that this bit only controls SERR
messaging for the Device 0. Device 1 has its own SERRE bits to
control error reporting for error conditions occurring on their
respective devices. The control bits are used in a logical OR
manner to enable the SERR DMI message mechanism.
Address/Data Stepping Enable (ADSTEP):
Address/data stepping is not implemented in the MCH, and this
bit is hardwired to 0. Writes to this bit position have no effect.
Parity Error Enable (PERRE):
PERRB is not implemented by the MCH and this bit is hardwired
to 0. Writes to this bit position have no effect.
VGA Palette Snoop Enable (VGASNOOP):
The MCH does not implement this bit and it is hardwired to a 0.
Writes to this bit position have no effect.
Memory Write and Invalidate Enable (MWIE):
The MCH will never issue memory write and invalidate
commands. This bit is therefore hardwired to 0. Writes to this
bit position will have no effect.
Special Cycle Enable (SCE):
The MCH does not implement this bit and it is hardwired to a 0.
Writes to this bit position have no effect.
Bus Master Enable (BME):
The MCH is always enabled as a master on DMI. This bit is
hardwired to a 1. Writes to this bit position have no effect.
Memory Access Enable (MAE):
The MCH always allows access to main memory. This bit is not
implemented and is hardwired to 1. Writes to this bit position
have no effect.
I/O Access Enable (IOAE):
This bit is not implemented in the MCH and is hardwired to a 0.
Writes to this bit position have no effect.
Host Bridge Device 0 - Configuration Registers (D0:F0)
Description
Datasheet