QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 6

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

6.2.19 C0AIT - Channel 0 Adaptive Idle Timer Control ......................................... 137
6.2.20 C0GTEW - Channel 0 (G)MCH Throttling Event Weight ............................... 137
6.2.21 C0GTC - Channel 0 (G)MCH Throttling Control .......................................... 138
6.2.22 C0DTPEW - Channel 0 Dram Rank Throttling Passive Event Weights ............ 139
6.2.23 C0DTAEW - Channel 0 Dram Rank Throttling Active Event Weights .............. 140
6.2.24 C0DTC - Channel 0 Dram Throttling Control ............................................. 140
6.2.25 C0DMC - Channel 0 DRAM Maintenance Control ........................................ 141
6.2.26 C0ODT - Channel 0 ODT Control ............................................................. 142
6.2.27 C1DRB0 - Channel 1 DRAM Rank Boundary Address 0 ............................... 142
6.2.28 C1DRB1 - Channel 1 DRAM Rank Boundary Address 1 ............................... 142
6.2.29 C1DRA0 - Channel 1 DRAM Rank 0,1 Attribute.......................................... 142
6.2.30 C1DCLKDIS - Channel 1 DRAM Clock Disable ............................................ 142
6.2.31 C1BNKARC - Channel 1 DRAM Bank Architecture....................................... 143
6.2.32 C1DRT0 - Channel 1 DRAM Timing Register 0 ........................................... 143
6.2.33 C1DRT1 - Channel 1 DRAM Timing Register 1 ........................................... 143
6.2.34 C1DRT2 - Channel 1 DRAM Timing Register 2 ........................................... 143
6.2.35 C1DRC0 - Channel 1 DRAM Controller Mode 0........................................... 143
6.2.36 C1DRC1 - Channel 1 DRAM Controller Mode 1........................................... 144
6.2.37 C1DRC2 - Channel 1 DRAM Controller Mode 2........................................... 144
6.2.38 C1AIT - Channel 1 Adaptive Idle Timer Control ......................................... 144
6.2.39 C1GTEW - Channel 1 (G)MCH Throttling Event Weights.............................. 145
6.2.40 C1GTC - Channel 1 (G)MCH Throttling Control .......................................... 146
6.2.41 C1DTPEW - Channel 1 DRAM Rank Throttling Passive
Event Weights ...................................................................................... 147
6.2.42 C1DTAEW - Channel 1 DRAM Rank Throttling Active Event Weights ............. 148
6.2.43 C1DTO - Channel 1 Throttling Observation ............................................... 149
6.2.44 C1DTC - Channel 1 DRAM Throttling Control............................................. 149
6.2.45 C1DMC - Channel 1 DRAM Maintenance Control ........................................ 149
6.2.46 DCC - DRAM Channel Control ................................................................. 150
6.2.47 WCC - Write Cache Control .................................................................... 151
6.2.48 MMARB0 - Main Memory Arbiter Control_0 ............................................... 151
6.2.49 MMARB1 - Main Memory Arbiter Control_1 ............................................... 151
6.2.50 SBTEST - SB Test Register ..................................................................... 151
6.2.51 ODTC - On Die Termination Control ......................................................... 152
6.2.52 SMVREFC - System Memory VREF Control ................................................ 152
6.2.53 DQSMT - DQS Master Timing.................................................................. 152
6.2.54 RCVENMT - RCVENOUTB Master Timing ................................................... 152
6.2.55 C0WL0REOST - Channel 0 WL0 RCVENOUT Slave Timing............................ 153
6.2.56 C0WL1REOST - Channel 0 WL1 RCVENOUT Slave Timing............................ 153
6.2.57 C0WL2REOST - Channel 0 WL2 RCVENOUT Slave Timing............................ 153
6.2.58 C0WL3REOST - Channel 0 WL3 RCVENOUT Slave Timing............................ 153
6.2.59 WDLLBYPMODE - Write DLL Bypass Mode Control...................................... 154
6.2.60 C0WDLLCMC - Channel 0 WDLL/Clock Macro Clock Control ......................... 154
6.2.61 C0HCTC - Channel 0 Half Clock Timing Control ......................................... 154
6.2.62 C1WL0REOST - Channel 1 WL0 RCVENOUT Slave Timing............................ 155
6.2.63 C1WL1REOST - Channel 1 WL1 RCVENOUT Slave Timing............................ 155
6.2.64 C1WL2REOST - Channel 1 WL2 RCVENOUT Slave Timing............................ 155
6.2.65 C1WL3REOST - Channel 1 WL3 RCVENOUT Slave Timing............................ 155
6.2.66 C1WDLLCMC - Channel 1 WDLL/Clock Macro Clock Control ......................... 156
6.2.67 C1HCTC - Channel 1 Half Clock Timing Control ......................................... 156
6.2.68 C0DRAMW - Channel 0 DRAM Width ........................................................ 158
6.2.69 G1SC - Group 1 Strength Control ............................................................ 158
6.2.70 G2SC - Group 2 Strength Control ............................................................ 159
6.2.71 G3SC - Group 3 Strength Control ............................................................ 159
6.2.72 G4SC - Group 4 Strength Control ............................................................ 159
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Datasheet